Flash memories are becoming increasingly popular. However, some persistent drawbacks exist with conventional flash memories. For example, many conventional flash memories employ a large block erase limitation that is capable of erasing no less than a block of the memory at a time and re-programming the entire block with new data, even if only a small portion of the block needs to be re-programmed. Due to this relatively large re-programming technique, conventional flash memories are slow to respond and cannot achieve a large number of erase/program cycles due to the stress on the memory cells inherent in the erasing and programming cycles.
Another limitation is that flash transistor erasing time is exponentially longer with a less negative erase voltage or a lower transistor threshold voltage. This is because the electric field in the transistor that causes the electron transfer to the floating gate will vary based on the applied voltages and the transistor threshold voltage. For example, the time required to erase a flash transistor will be longer if -9 V is applied to the gate rather than -10 V. And, for example, the time required to reduce a flash transistor threshold (Vt) from 2 V to 1 V is approximately ten times the time required to reduce the threshold from 3 V to 2 V. Some techniques of reducing this time are by applying a greater negative voltage (e.g. &lt;-10 V) if the erase procedure is to remove electrons from the floating gate, or a greater positive voltage (e.g. &gt;15 V) to the wordline (transistor gates) if the erase procedure is to add electrons to the floating gate. Such techniques are described in U.S. Pat. No. 5,481,494 incorporated herein by reference. FIG. 1A shows a known technique that applies a fixed erase voltage of -10 V to the selected wordline (gate) for the entire erase procedure. Since the initial Vt is about 4 V greater than the final Vt after the completion of the erase procedure, the cell's tunnel oxide suffers the greatest electric stress at the beginning of the erase procedure, thus causing the hole trapping and oxide degradation. As a result, the flash transistor endurance is significantly reduced.
Another known flash memory, described in U.S. Pat. No. 5,485,423 incorporated herein by reference and shown in FIG. 1B, employs a stepwise decreasing voltage to the selected wordline (transistor gates) in order to reduce the possibility of hole trapping in the tunnel oxide and oxide degradation. This technique reduces the applied voltage in a stepwise fashion thereby reducing the high electrical field at the beginning of the erase procedure. Once the maximum negative voltage is achieved (e.g. -9.5 V), that voltage is applied until the erasure is complete. Although this technique significantly reduces oxide degradation, the erase time is still exponentially long when the lower erase threshold voltage (Vt) is required.
One feature common to the known flash memories of FIGS. 1A and 1B is that the deselected wordlines and sourcelines maintain a fixed voltage (e.g. 0 V) during the erase procedure. The wordline drivers of these circuits may experience significant stress due to the large voltage differential between the driven lines and the non-driven lines if the voltages of wordlines or sourcelines are increased. Such stress can cause device junction breakdown and may cause premature degradation or failure of the wordline driver.
The most negative or positive voltage of the selected wordline is limited by the maximum tolerance of the breakdown voltage (BVDSS) of PMOS and NMOS devices in the X-decoder wordline drivers. In particular, the BVDSS is determined by the voltage drop between two power supplies connected to M20a, M20b and M21a, M21b as shown in FIGS. 5A-B. The voltage drop across the two power supplies is equivalent to the voltage difference Vg(diff) between the selected wordline Vg(sel) and deselected wordline Vg(desel). If Vg(diff) exceeds the junction gated breakdown of the driver device (BVDSS), then large current will leak to the substrate until Vg(diff) drops to lower than (BVDSS). This is particularly relevant for thin oxide semiconductor devices which are conventionally used in flash memory circuits and where the maximum Vg(diff) is approximately +/-10 V. However, this voltage difference is not sufficient to provide fast erasing at low threshold voltages below approximately 3 V.
One further limitation of conventional flash memories is that the voltage across the cells' tunnel oxide is reduced when hole and electron trapping occurs after thousands of program and erase cycles. The wordline or sourceline voltages have to be increased to compensate for the electric field drop induced by the trappings.
Goals of the invention are to overcome the identified problems and to provide a new technique to quickly erase selected portions of the flash memory and improve the life of the flash memory.